Complex circuits of serial links and parallel buses – digital signal matching within such circuits

It is worth stipulating from the outset that my publications still relate to an opinion, and not a tutorial, and were followed, up to and including this one, due to shortcomings and error corrections. Because I am guided, first of all, by a textbook on circuit design (“Digital Circuit Design by M.A. Shustov”), for those interested – there will be a lot of quotes and diagrams from the book, and the vision of circuit design by FPGA manufacturers or its necessary amendments for the purposes they need (and most importantly – write the code, and you may already be able to select a suitable chip configuration, even if this does not happen – nothing, I’ll wait until they start producing boards of the required configuration, and before that I will further develop and work on the project with those boards that are commercially available) I think still secondary, although it will be necessary to study. There are no matching resistors in the FPGA – which prevents the implementation of a number of circuits, but there is something to replace them for a digital signal inside such circuits. I tried to find on the network an alternative to a matching resistor for use inside the synthesized circuit, the search engine returned a modest search result, the content of which turned out to be nothing of substance – categorically no on all forums, and sometimes something close, but not decisive for my task. And in fact, two tasks are deployed in the scheme – a certain cache of a new type and a mechanism for managing such a cache, in fact – part of a new type of processor.

There's a lot to delve into the design. If you do not believe the Logisim Evolution IDE, you can simply pass by and not take the material presented here into something necessary and useful. Moreover, this is, in general, the work of a beginner who is simply developing his project and views in new areas, encountering new problems and solving them in new ways. Therefore, until I have studied the subject sufficiently, all this remains in the “opinion” category. And in the final processor implementation, the bridge cache functionality can be deployed, since it was not specified anywhere what kind of trigger it is RUN and in principle, its contents can be changed from zero to one through the command cache address decoder, if each such trigger is tied to a bridge cache link to launch it. That is, unnecessary bridge cache cells, even if the signal passes directly through the keys, can also be skipped by starting it from the desired point (the keys also do not work instantly).

Next, it is worth apologizing to the reader for writing about instantaneous actuation on logical elements, where it did not exist by definition; I used their icons and simulation to speed up debugging and create circuits – it’s faster with them. Now, after some debugging, I use the icons that are according to the digital circuitry.

What do you mean by icons?

This means an electronic key or, as they also call it, an electronic key element. Further, where necessary, I provide quotes from the book “Digital circuitry” the basics of construction from the basics to the heights of mastery, author Shustov M.A. But I give a little more than I use for my own purposes, I give explanations on this subject. You can skip this under the spoiler, since it has nothing to do with the processor project, and in any case, I will not leave the project, since there are too many tools and ways to make the bridge cache very effective.

Based on the fact that under the spoiler, the optimism of this activity with its own processor is not very high, but nevertheless, taking into account that all the key elements in the operation of the circuit require a high speed of signal transmission without stopping (depending on the state of each next link in the chain – the link is skipped or put into operation) are switched to the on state long before the required signal propagation time and the fact that the functionality of the bridge cache can be significantly expanded, we can nevertheless hope for some positive effect, and not even a bad one.

When I was faced with the problem of more accurately debugging two mechanisms on the circuit, I discovered that a matching resistor was needed, without it everything seemed to work, but the mere thought that an error condition was flashing on some wires, the feeling of a completed job quickly disappeared.

And why I still haven’t started working with my board – because I first had to fix all the shortcomings and errors.

Next is the corrected bridge cache.

There are still only two triggers per link in the bridge cache chain (and functionality that is not yet expandable). A bridge cache chain link is a circuit cell that activates a command cache memory cell without resorting to the operation of a command address decoder. In the diagram, the command cache memory cell is simply indicated by an activated LED.

Well, first of all, why has it been fixed? I think that it is more promising to use electronic keys than logical elements, because they will operate faster. Of course, this depends on the type of keys – on what logic elements they are implemented, and in general, logical elements, as I understand it, are a little more complicated and their response time is longer. And even if this is not the case, and if the basic logical elements are not much more complex than a switch, triode or transistor, then there is no guarantee that the Verilog compiler will connect the legs on the buses exactly as needed and performance will not be lost, in addition V In electronic keys there is a floating signal at the output, and as it is repeated it can accumulate into an error, so it is certain that the basic logical elements are much more complex than electronic keys.

And so they wrote to me that no, this is not like that. Yes, this is so, before you write this, you should try at least one circuit with its own bus in the simulator and immediately be convinced that the electronic key is much simpler than the basic logical element. And repeating someone else’s well-functioning schemes and contemplating them in simulators will never give a complete picture and idea. And to those who write that you don’t need to draw circuits or even make your own processor, since absolutely everything can be implemented on an FPGA, I’ll say – well, since everything is so simple, write in Verilog for an FPGA… any CAD, OS, or at least full-fledged Blender 3D. Once you do it, be sure to write about it to others.

Secondly, without electronic keys it is difficult to connect links to the chain bus and make them work without errors. This was discovered after debugging the mechanism for filling the bridge cache, and in the “stub” diagram, errors resulting from repetitions of the floating signal are marked separately as the very first, and then the second. The second ones were made simply out of a desire to do everything as it should and to finalize the circuit, even though it worked like that, but I wanted the error signal not to arise during operation of the circuit.

and that's all. The bottom part of the diagram, separated from the top by blue segments located horizontally, displays the mechanism for filling the bridge cache. At the top is the bridge cache itself. Error plugs are a painstaking task, since the method is neither systematized nor formalized to the level of technology, and each type of chain link at the place where it occurs requires its own approach and solution, and I have not reached the algorithm for finding the place of insertion and the type of plug.

How it works (how error stubs work – everyone can check for themselves).

First in the trigger line Last (from the trigger labeled Last to the right in the diagram), which is a constraint on filling line triggers Memo, a unit is recorded, this is done by applying a signal to the very bottom row of the contact, and a unit signal to the contact of the lowest horizontal wire (I did not fill the diagram with labels, since this will probably make it very difficult to read). After which these one signals change to zero again. Then, if necessary, it is installed in the trigger with the label FillingBridges values ​​that we need to fill into triggers Bridge bridge cache at the top scheme. If the trigger or triggers are filled with one, then during the operation of the bridge cache the corresponding LED will light up, which is equivalent to calling the corresponding command cache cell. If zero, then the link and its corresponding command cache cell will be skipped. The filling process can be repeated if necessary. Next, the unit signal is removed from the contacts of the filling mechanism. Next to the trigger Run a unit is written to give a signal through the wire to cycle through the links of the chain. Then click on Button_1 into triggers Start a unit is written, if a link is skipped, then during the operation of the bridge cache it will remain, if it calls a command cache cell, it will be replaced by zero. To view the simulation step by step you need to Logisim Evolution uncheck “Simulation enabled” and the element selection pointer (hand cursor) in the trigger Tact set unit. Next press CTRL+I, as a result of which the first LED in the link will blink, and the trigger Tact the value will be set to zero. So until the entire chain has passed. The skipping of links with zero in the trigger is carried out autonomously. After the end of the chain, the procedure can be pressed again and written to the triggers Start units.

Now, after I have eliminated all the shortcomings in the circuit, all I can do is work with the FPGA, of course this is during periods of free time from the main and other matters. I will be glad if my experience is useful to someone in other decisions. Now there is definitely nothing to write except the results of working with the FPGA. Thank you all for your attention… and understanding if I accidentally took up their time. Don't expect quick answers from me – I have a long working day, etc. And I hope that there is no need for comments, since the turn of Verilog and the next results has just arrived.