x86 is out of work, ARM has broken both legs

Hello, regular and not so regular readers 🙂

It's me again – with the fourth article in the series about architectures, processors and all that. Let me remind you how it all happened:

• Part I: Scandalous revelation of x86: ARM bursts in with two legs

• Part II: This industry needs a new hero: ARM is jumping in with both feet

• Part III: Chinese kidnapping: daughter kidnapping

• Part IV: RISC-V – a star is born: x86 is out of business, ARM has broken two legs ← YOU ARE HERE

  Since then, a lot of liquids have flowed under the bridge: titanic shifts in x86 due to Intel’s failures with massive processor failures (they say that Qualcomm may even buy them, no one would have believed this a couple of years ago); ARM – architecture as a whole – has slowed down with its Gulliverian steps from generation to generation, even in the server segment everything has somehow become quiet (we don’t see mass-produced Dell or HPE servers with ARM chips as our ears); the Chinese atXThey vatized the IP (Intellectual Property) layers from the British and quietly developed their microelectronics under sanctions, without interfering with anyone.

  As you can see, there are a lot of interesting things; for a better immersion in the context, it’s worth reading the first three articles in the series (at least glance at it), but this is at your discretion. My job, after all, is to make sure that you don’t fall asleep on your lunch break over a cup of coffee, and therefore this longread is readable even without a “Silmarillion” under your belt.

What's RISC: X-Men and Backstory

RISC-V (pronounced “risk-five”») is an open, modular processor architecture and instruction set introduced in 2010. By the standards of other architectures, this is literally yesterday (x86 in 16-bit form was born in 1978).

This wonderful architecture was born in the (hopefully underground) laboratories of the University of California at Berkeley. It is based on the RISC (Reduced Instruction Set Computing) concept, just like ARM. RISC-V initially differed from similar projects in that it was planned for a variety of computing tasks, not just education.

Project large-scale, a whole group of scientists and engineers worked on it, but the main drivers of the project were two scientists (Oppenheimers in their field). Everyone knows Jobs or Gates, but many great minds are unknown to the general public – I will correct this misunderstanding.

Professor Xavier David Patterson – American scientist, professor of computer science at the University of California at Berkeley, Turing Award winner, genius, philanthropist, billionaire. He was at the forefront of the development of RISC architecture back in the 1980s, so we can thank this man for ARM. Patterson coined the term RISC and played a key role in developing the concepts that formed the basis of RISC-V. A bit of offtopic information: he also participated in the creation of RAID array technology, without which it is difficult to imagine modern servers.

Krste Asanovic is a scientist-engineer, PhD in computer science at Berkeley, co-founder of SiFive (a fabless semiconductor company developing commercial RISC-V processors and IP blocks for them). He was one of the lead architects of the RISC-V project. Asanovich and his students in the laboratory developed the first RISC-V specifications and began actively promoting the idea of ​​open architecture.

I will note another scientist-engineer – who was the co-leader of the RISC-I project – Carlo Sequina. In the 1980s, the very idea of ​​reducing the length of commands seemed quite radical. Sequin, along with other engineers at the University of California at Berkeley, created a scientific basis that showed that it was possible to achieve significant acceleration of processor operation due to a simplified instruction set architecture.

When creating RISC-V, engineers were aiming for something fundamentally different—an open architecture that could be freely used and modified. David Patterson and Krste Asanovic released a technical report “Instruction sets should be free: the case for RISC-V” – the name speaks for itself.

The attentive reader will probably have a question: okay, RISC-V, what about the first 4 versions? 5 rather indicates not a version, but rather a historical continuity and improvement of previous developments of the ancestral architecture of RISC and other similar technologies.

• Berkeley RISC (1980-1984): The first version of the architecture, developed at Berkeley under the direction of David Patterson and his team. As a result, an experimental processor appeared RISC-I (44,420 transistors) with a simplified instruction set (32 instructions), which was able to prove the effectiveness of the RISC concept compared to traditional CISC architectures. A couple of years later he appeared RISC-II (40,760 transistors) is an improved version of the RISC-I processor with a larger instruction set (39) and approximately 3 times the performance of RISC-I.

The project showed that simple architecture can be functional and efficient. For authenticity, I note that even before the name RISC appeared, there were already devices that could be attributed to this concept: CDC 6600, Data General Nova, IBM 801 family of processors. But it was the project Berkeley RISC gave the name to architecture. The project was later commercialized by Sun Microsystems – this is how SPARC was born; RISC also inspired the ARM architecture.

• Stanford MIPS: Work on this architecture for research purposes was carried out in parallel at Stanford from 1981 to 1984 under the direction of John Hennessy. Something of an answer to RISC and the IBM 801, this work became the foundation for MIPS Computer Systems and the commercial MIPS family of processors that were widely used in the industry (for example, the R2000 microprocessor): embedded computers, PCs, workstations, servers and supercomputers.

• SPARC: SPARC (Scalable Processor Architecture) was developed by Sun Microsystems based on RISC concepts in the late 1980s. SPARC was widely used in workstations and server systems.

  RISC-V already at the concept stage it was conceived as something capable of turning the microelectronics market upside down. Let me emphasize that it can, but will not necessarily do this: good technology/idea alone is not enough for dominance survival in the market, otherwise Windows Phone would not have died ingloriously. That being said, RISC-V is not a concept; it has proven its viability in real products. But more on that later.

  Openness, modularity and customization are three tightly knit pillars of RISC-V that are not available to corporate mastodons like ARM Ltd., Intel and AMD.

The first is openness.

The full RISC-V specification is available to everyone. This architecture is not bound by licenses, patents and other capitalist-gilded tinsel. If Steve Wozniak wished Santa anything for Christmas, it would be this approach in microelectronics. Any company – from a startup to the once-cyclopean IBM – can use RISC-V for 0 shekels. And that's good. But what else does RISC-V have up its sleeves?

Modularity and customization

The RISC-V Basic Instruction Set—aka ISA, the minimum instruction set that is supported by all RISC-V-based processors — can be supplemented with standard or custom extensions. This allows you to create specialized processors for specific tasks without losing compatibility with other processors.

The basic set supports all standard operations: arithmetic/household register calculations, memory management (load/store), I/O operations and synchronization of multitasking processes. Vendors can add or remove functional blocks/modules for graphics processing, database or AI work, minimizing unnecessary instructions and legacy tail. They can be created from scratch; you can take open free solutions; you can license someone's proprietary solutions. This is an extremely effective and flexible approach.

For example, I’ll give Rocket Chip (Here about him in detail) is an open-source system-on-chip (SoC) design framework developed by a team at Berkeley based on RISC-V. In essence, it is a customizable and flexible foundation (platform) for the design and creation of high-performance processors. Includes basic RISC-V cores that support caching, multithreading, and even advanced neural network instructions.

Where is RISC-V's place in the sun?

You've probably heard about the concept ASIC (Application-Specific Integrated Circuit, integrated circuit for a specific application). Nowadays, ASIC devices are usually used for one task, for example, mining cryptocurrencies or processing data packets, bypassing the CPU.

The first ASICs appeared back in the 1970s, companies developed integrated circuits for specific tasks – large volumes of calculations, where simplicity and speed are more important than versatility; Yes, this greatly limited the functionality, but they were cheaper in terms of performance in specific calculations: mathematical operations, process control, signal filtering and information decoding.

In general, ASICs are forerunner technologies.

The heyday of ASICs came in the 1980s – the times of Michael Jackson, Star Wars (those terrible ones); the beginnings of the Internet in the form of ARPANET, the first mobile phones in suitcases. ASICs have taken root in telecommunications, computer systems, and industrial automation.

In the slow 1990s (in the States, that is), the technology was optimized and made cheaper thanks to EDA (design automation) tools, and already in the 2000s the real juice began. More precisely, SoC (System-on-a-Chip, SoC) is a system on one chip. When designing, we learned to place several functional blocks in one chip: computing cores (general-purpose application processor), memory, I/O interfaces and other components, which not only reduces the cost of production, but also reduces power consumption. To this day, SoC is the industry standard. All modern ASICs have become SoCs, and all SoCs are essentially ASICs with auxiliary blocks. ASICs – as individual devices – continue to be used in AI, 5G, autonomous systems, cryptomining, etc.

But what does RISС-V have to do with it?

The market is dominated by x86 and ARM. The first has a monopoly in desktop and server systems (ARM's share is insignificant) and a legacy tail the size of Yakutia; the second has a monopoly in mobile and embedded systems, as well as strict licensing and standardization for compatibility (ANE can be screwed in, but a significant part must be the same as it was developed by ARM Ltd.).

RISС-V wins in many respects: there is no giant legacy tail; there is no strict standardization of cores, as in ARM (but this is also a problem for optimization); the entry threshold for a potential vendor is significantly lower than in x86 (there is essentially no one except Intel and AMD); licensing blocks from third-party developers upon request; ease of development of new microcontrollers or processors.

RISС-V looks especially advantageous in highly specialized solutions: ASIC, SoC with blocks for solving specific tasks, microcontrollers / MCU (MCU in the context of SoC means the inclusion of a microcontroller unit in a larger integrated circuit design), IoT (Internet of Things, Internet of Things).

Major players like Alibaba and Google have already become involved in the development of architecture. Google, by the way, creates proprietary Titan security keys for cloud services and devices that contain a RISC-V cryptoprocessor. They also have Titan M2 for Pixel smartphones on RISC-V – this is a separate chip (SoC-ASIC) that does not use the resources of the main processor. Something like a TPM (Trusted Platform Module) module in motherboards (the thing that is required to install Windows 11 is also about security).

And it is especially important that Google plans make RISC-V a “tier-1” architecture for Android. And this is already a serious request.

RISC is everywhere

RISC-V creates unique conditions for development: openness, flexibility and adaptability at the hardware level, independence from politics, sanctions, etc. With sanctions, I’ll clarify: since RISC-V is open, the international community is extremely important; direct sanctions are impossible, but you can declare a country (or any research institute) not to shake hands – and none of the bright democracies will risk starting joint projects or selling licenses for their IP. States insert a spoke in China's wheels and they will insert it to everyone else they want. Russia has already created its own association “RISC-V Alliance”.

Conglomerates and corporations that can afford research and development, as well as order the production of a more or less large batch of chips at TSMC or at a factory with an outdated technical process (3-nanometer chips are not needed everywhere), develop their own custom solutions based on RISC- V – so there is more control (no hardware security for you) and freedom from licensing. Although in practice, developing a complex SoC on RISC-V from scratch does not make sense for most companies – there are ready-made open or paid IP (Intellectual Property) “cubes,” modules that can be taken for free or licensed and used for your system on a chip: processing units, interfaces, memory controllers and other components that developers integrate into their SoCs rather than designing them from scratch.

Examples of RISC-V products

Qualcomm and their microcontrollers; Alibaba and their XuanTi processors; SiFive and their 64-bit multi-core chips (even Linux distributions work); DeepComputing sells laptop DC-ROMA Laptop IItablet DC-ROMA Pad II for native development and other products. Semidynamics has introduced the world's first fully coherent RISC-V tensor block.

In addition, we should not forget about independent developers and research institutions that are actively using RISC-V in education and research. RISC-V allows engineers and programmers to design chips without bureaucratic restrictions. This means there will be an influx of new ideas and unusual solutions that are difficult to implement in closed systems.

Of course, RISC-V is considered as a technology for space programs and military systems: the European Space Agency (ESA) is studying – and maybe already using – this architecture to create processors in space devices. The openness of RISC-V allows us to avoid total dependence on American/English technologies, which seems to be critical in the face of possible sanctions or geopolitical restrictions (I’ll leave my comments to myself, but apparently even the Europeans have a plan B somewhere or a plan for the last letter of the English alphabet) . Russia, by the way, is also investing in the potential of RISС-V, although we also have our own Elbrus.

China is actively developing RISC-V in its projects, including in the field of space technology – there are no questions about that. In the USA, solutions are being developed based on RISC-V for military electronics and autonomous systems. Nothing surprising either.

To summarize, RISC-V is developing in breadth and depth, while x86 has gotten worse (I hope Intel will cope with the problems, we need competition), and ARM has slowed down. There are already real products based on RISC-V, yes, niche ones, but there is enough potential for PCs, game consoles, smartphones, servers, etc.

Not conclusions, but problems

I see a bunch of barrier walls for RISC-V. If advanced developments are in the military and space industries (and this usually happens), then no one will share them – even years later. If China or Russia, under sanctions, will create advanced RISC-V chips, then why share the license for the blocks with “unfriendly” countries? If a corporation like Apple develops an equivalent of its M-chips on RISC-V, then neither Google, nor Samsung, nor Microsoft, nor anyone else will ever see them (to be fair, there are no current A and M-chips on ARM either no one has, only competing chips from Qualcomm and MediaTek).

Fragmentation will be significant (this is both a challenge for compatibility, but also flexibility when creating specialized solutions, such as ASIC) + difficulties with cybersecurity, but this is not necessarily a bad thing, proprietary modification blocks from corporations that have both been and will be their IP; Only chips compatible with common user and server operating systems will go there. But corporations will not have a complete monopoly on everything; startups and small companies will appear that, without their own products and production facilities, will create excellent modules for RISC-V processors.

And the result is maximum freedom. If you want, create your own from 0; if you want, take something from the open options; If you’re not satisfied, make a hybrid or license blocks from third-party companies. The entry threshold will become easier, the influence of politics will be less, and there will be more new ideas. If now it is difficult to imagine the emergence of a third party in the x86 world, then in RISC-V this will be possible even with one global hegemon.

RISC-V is not just a technological alternative to the dictates of x86 and ARM Ltd. This is a new philosophy of processor design: open, adaptable and reducing development costs. A kind of designer for everyone, Open Source in the world of microelectronics, if you like.

All that's left to do is a complete ecosystem, full support for modern operating systems and compatibility with existing popular software. Effective emulators, like Rosetta, are suitable at the initial (hopefully, transitional) stage, but native support will be more effective.

And RISC-V has everything to compete with x86 and ARM even in the mass segment.