# What does a topologist have in common with an artist and what does lithography have to do with it

Topology design is one of the key steps in the development of integrated circuits. This can be called an art, since the regular decrease in geometric norms and the increase in the complexity of projects requires a lot of work from topological engineers. And of course, this specialty was not ignored at the hackathon.

Hi, I’m Alexander Kalyonov, a graduate student and engineer at the Department of Integrated Electronics and Microsystems at MIET, I work as a VLSI designer at NIIMA Progress. For the YADRO SoC Design Challenge hackathon, I created a topology task, which we will consider here.

## For those who are here by chance, or About the topology on the fingers

*$170 million ASML photomask lithographer*

## Will robots replace topologists?

*Open in full size, keeping in mind that it is “drawn by hand”.*

So why do we need human participation, why can’t everything be entrusted to a machine? And the answer is simple – by the car **bye** there is no technical ability to design a microcircuit on your own.

For example, when designing power and ground rails, the thickness of these rails must be taken into account, since current flows there. If you make a thin bus, then when you turn it on, the circuits will immediately burn out. Especially if the consumption there is several hundred milliamps. There were such cases that many circuits were produced, which, when turned on, immediately burned out and there was no way to check them.

At the current stage of development, the machine cannot correlate the current that flows with the thickness of the busbar that needs to be made. Therefore, it is calculated by a person. We can say with confidence that in the foreseeable future, topologists do not need to be afraid of the “invasion of robots”.

## And what about the task?

The topology task was as close to practice as possible and was divided into three parts. The first two are related to digital topology.

First, the participants had to assemble the D-flip-flop, DV-flip-flop, and microwave dongle circuits using the gpdk045 DDK library (gsclib045). Then create their symbols, a test circuit to check the functionality and design the topology. Then sequentially carry out first DRC and then LVS verification and extraction of the topology of the developed triggers and the key, which had to be taken into account in subsequent modeling. Then the differences began.

**Detailed text of tasks**

**Exercise 1**

- Using the gpdk045 (gsclib045) DDK library, assemble the D-flip-flop circuit.
- Create a D-trigger symbol.
- Create a test circuit to test the functionality of the D-flip-flop
- Design topology of D-flip-flop
- Carry out DRC verification
- Verify LVS
- Carry out the extraction of the topology of the developed D-flip-flop.
- Carry out simulation of the D-trigger taking into account the extraction
- Design a frequency divider circuit (by 2, 4, 8, 16, 32) using the developed D-flip-flop.
- Generate frequency divider symbol (by 2, 4, 8, 16, 32)
- Create a test circuit to test the performance of the frequency divider (for 2, 4, 8, 16, 32)
- Design the frequency divider topology (by 2, 4, 8, 16, 32)
- Carry out DRC verification
- Verify LVS
- Carry out the extraction of the topology of the developed dividers
- Simulate the frequency divider (by 2, 4, 8, 16, 32) taking into account the extraction

**Task 2**

- Using the gpdk045 (gsclib045) DDK library, assemble the DV flip-flop circuit.
- Create a DV trigger symbol.
- Create a test circuit to test the functionality of the DV flip-flop
- Design DV flip-flop topology
- Carry out DRC verification
- Verify LVS
- Carry out the extraction of the topology of the developed DV flip-flop.
- Carry out DV-trigger simulation taking into account extraction
- Design a circuit for a non-cyclic reversible counter from 0 to 8: using the developed DV flip-flop.
- Create a symbol for a designed counter
- Create a test circuit to test the performance of the developed counter
- Design the meter topology
- Carry out DRC verification
- Verify LVS
- Perform meter topology extraction
- Carry out simulation of the counter taking into account extraction

**Task 3**

- Using the technological library gpdk045, assemble a microwave key circuit (GPT-shaped) to obtain the lowest losses and the highest isolation.
- Create key symbol
- Create a test circuit to test the functionality of the key
- Design Key Topology
- Carry out DRC verification
- Verify LVS
- Extract the topology of the developed key.
- Carry out key modeling taking into account extraction

For the part with a D-trigger, it was necessary to design a frequency divider circuit (by 2, 4, 8, 16, 32). For the part with the DV trigger, design a circuit for a non-cyclic reversible counter from 0 to 8. The part with the assembly of the microwave key circuit did not hide surprises in itself, but, unfortunately, none of the participants got to it. Because of this, the jury had to evaluate those who coped with the first two parts to the maximum.

To create a division cell by two, by four and by eight, participants tried to use a latch (half master / slave), trying to reduce their work by implementing it on a simple circuit. In a good way, it was necessary to use the master / slave trigger scheme.

It took the guys a lot of time to search for a suitable solution on the net. If the implementation of the divisor by two can still be found, then here is the transition to dividing by four and by eight – you need to think it out yourself. Especially in the second part, where it was necessary to design the counter circuit. For her, it was necessary to write a truth table and assemble a digital block from it, and the students decided that they could google it.

Another reason why the participants did not manage to solve 3 parts is that they did not work with this development environment. Only written design instructions helped them to complete the first two parts of the task and correctly implement the topology.

## We wind experience on a mustache

From the participants’ problems with the third task, the organizers learned an important lesson about informing the participants in advance about what they will work with.

Initially, the task was created for those who saw the Cadence Design System and are aware of how to design topologies there. MIET has departments of microchip design that teach how to work in this program. Fourth-year students from the Department of Topology Design could, after thinking, write a truth table. But it just so happened that only one participant came from this department to the hackathon and the teams had to improvise, in this they were helped by their experience in designing boards, which can be correlated with chip design. After all, if a person understands how resistors or capacitors are connected on the board, then he can, after a little thought, do this on a microcircuit.

How to fix such an imbalance of participants, we will still think. For example, you can hold a series of webinars that would detail the role of topology in chip design and talk about tools, the same Cadence Design System.

Despite some difficulties, the participants noted that they liked the task and would like to participate again. It remains only to promote this and to interest more young people in topology, especially since the demand for topologists will only grow due to the opening of new design centers in Russia.