We will discuss optimizations for architecture and performance monitoring tools
If you are interested in the development of open processor architecture or are already developing something for it, join the evening meetup of the Russian RISC-V and YADRO Alliance on Wednesday, November 6th. Together with experts from Syntacore, UNN. Lobachevsky and YADRO we will discuss the latest news in free architecture: from cyclic optimizations and scalable vectorization to the prospects for hardware monitoring and performance analysis in RISC-V.
We have prepared a surprise for offline participants: the meetup will take place in the very center of the city – the Nizhny Novgorod Kremlin. But if you are far from the capital of sunsets, register to the broadcast and join online.
What's in the program
Loop Optimizations and Scalable Vectorization in RISC-V
Konstantin Vladimirov
Head of Development Tools and Compilers, Syntacore
Mark Goncharov
software engineer, Syntacore
Engineers will tell you how scalable vectorization works and how cyclic optimizations work in Syntacore Development Toolkit (SC-DT)such as cycle splitting, help achieve better results on benchmarks. They will also talk about developments in optimizing inductive variables. Finally, we will touch on the vectorization of library functions in the compiler using the open SLEEF library.
Optimizing the CatBoost library to use RISC-V vector extensions
Joseph Meerov
Head of the Department of High Performance Computing and System Programming, ITMM Institute, UNN
CatBoost is a toolkit for gradient boosting on decision trees. In the talk I will provide an overview of the optimizations of this library for effective use of the RVV 0.7.1 vector extensions for RISC-V. I will show a methodology for identifying performance bottlenecks without developed tools, and also tell you how to use intrinsics and manual vectorization in computationally expensive loops when the compiler cannot generate optimal code.
Improvements implemented by a group of researchers from UNN. Lobachevsky, will speed up calculations on a specific implementation of the RISC-V platform several times.
Current State and Outlook for Hardware Monitoring and Performance Analysis in RISC-V
Dmitry Ryabtsev
software development expert, Syntacore
I will tell you what monitoring capabilities already exist and are actively used in existing RISC-V systems. They help to effectively find and fix bottlenecks in software, system settings and processor microarchitecture. I will also highlight which features have been recently added, which are being developed or planned to be implemented in the near future.
The foundation of the report is the result of the work of two groups in RVI: Performance Analysis SIG and DTPM SIG, as well as a number of their technical subgroups, in which all the work on specifications for monitoring is carried out.
Where and when do we meet?
November 6, Wednesday. The conference starts at 19:00, gathering of guests starts at 18:30.
In Nizhny Novgorod: Kremlin, building 6 (Arsenal), Gorkovskaya metro station. Entrance by registration – you need it to secure your place in the hall.
Online: we will send a link to the broadcast on VK, YouTube or Rutube after registration on the website.
