The developer of the Russian RISC-V kernel will teach schoolchildren and students RISC-V assembler on Saturday
The next session will be held on Saturday, November 13 from 12.00 Moscow time Skolkovo School of Synthesis of Digital Circuits, in online mode. According to the plan, it was supposed to be exercises on an FPGA board with sequential logic. However, we decided to change the plan and move the lesson on RISC-V architecture to that date. This activity was originally scheduled for December 11th. The Sequential Logic lesson will be moved to 20 November. Why we decided to do this – see the explanation in three paragraphs.
The RISC-V lesson will be conducted by Nikita Polyakov, a Russian microprocessor core designer, from Syntacore. Nikita moved to Syntacore from MCST where he designed the Elbrus processor.
The lesson will consist of a lecture with simultaneous exercises on the simulator RARS… RARS simulates the processor at the architecture level (a set of instructions visible to the programmer), in contrast to the Icarus Verilog simulator, which we discussed in the previous post and which simulates at the register transfer / microarchitecture level (the internal structure of the processor circuit). The processor designer needs to be able to use both types of simulators.
RARS has three buttons – run, assemble and execute a step. At the end of this lesson, you will be able to program in assembly language, even if you have never done it before. In this post, we will show you how to install the simulator and run a simple assembly language program. Then in the next post I will write what is so special in the RISC-V architecture and why we chose it for the seminar, and not ARM, x86 / 64, MIPS, AVR, SPARC, Elbrus, Z80, 6502, PDP-11 or else something else.
But above all:
Why did we decide to change the schedule?
We planned a rather intimate action in a room in the Skolkovo Technopark for 25 people, for which we bought 25 boards and 25 sets of peripheral devices.
At the same time, we planned a logical sequence: an introduction to the simplest schemes – more complex schemes – a processor – an adult route for an ASIC – schemes at the company interview level.
We received 310 applications.
Despite the fact that in addition to the 25 boards we ordered more than 100 boards, these boards are still coming from China and most of them will not arrive by November 13, but will most likely arrive by November 20.
At the same time, we have on hand about 80 emails from participants with certificates of the Rosnan course and more than 10 solutions of the first series of exercises on the verilogue. We will send and distribute payments in Moscow to everyone who has no pay and who completed these prerequisites (Rusnano or two series of exercises on the verilogue), but we will not have time to do this until November 13.
Rescheduling the RISC-V lesson to November 13th is a solution because:
This activity is done entirely on the RARS simulator and does not require an FPGA board.
This lesson also does not require knowledge of the verilogue – everything happens at the level of the instruction system, assembler, architecture – how the processor looks from the point of view of the programmer.
Then in December we will have the second part about processors – microarchitecture, how the processor is arranged from the inside. It will already require the synthesis of a processor on an FPGA board.
Of course, this solution has disadvantages:
There will be 4 weeks between the architecture lesson and the microarchitecture lesson, and knowledge of the second is necessary to know the first. Well, we will try to refresh the knowledge of the first one during the second lesson. In addition, understanding the idea of an assembler is like learning to ride a bicycle – once you have learned, you can repeat it all your life. Especially something as simple as RISC-V.
Another drawback is that with this lesson we interrupt the sequence about Verilog. To compensate for this deficiency, in the first hour of the lesson on November 13, not Nikita Polyakov will speak, but Aleksanlr Silantyev from MIET, who will analyze the problems that we presented to your attention a week ago.
You may immediately wonder where this RISC-V is used? In general, on the RISC-V architecture, you can build processor cores of different classes, from microcontrollers to desktops (which is now being developed by the Russian company Yadro Microprocessors) and to a supercomputer, but most of all RISC-V is now used in embedded applications. I don’t have a good photo of a built-in application with RISC-V at hand, but here is a photo with a built-in application based on the MIPS architecture, from which many ideas came to RISC-V (also ideas from RISC-I / II / SPARC, ARM and other architectures, from supercomputers to DSPs). To the left of Irina’s girl is a Japanese robot dog with a variant of the built-in MIPS R4000 microprocessor:
RARS is written in Java. If you don’t have Java runtine, here is instructions on how to install it for Linux, Windows and MacOS… Especially easy for Linux:
sudo apt-get --yes install default-jre
RARS itself is just one jar file that is downloaded here… You can also use a copy of the RARS from the current school activity package:
ChipEXPO 2021 Digital Design School package v2.3
Link via bit.ly – https://bit.ly/chipexpo2021dds23
Inside the package, RARS is located in the ce2020labs / day_3 / arch / risc_v_lab / directory. It’s called rars.jar. If it does not start in Explorer (for example, the file is associated with the archiver, not Java), run it in the command line:
java -jar rars.jar
Or click on the batch file ce2020labs day_3 arch risc_v_lab rars.bat in Windows Explorer. Or under Linux at ce2020labs / day_3 / arch / risc_v_lab / rars.sh.
After starting, you will see a window like this:
Press Ctrl + N or click on File | New and enter some program in RISC-V assembler, for example, this program for scheduling memory in a loop with Fibonacci numbers. Nikata Polyakov will teach you how to write such programs at the seminar:
li t0, 1 li t1, 1 li t2, 0x10010000 li t3, 64 loop: sw t0, (t2) sw t1, 4 (t2) add t0, t0, t1 add t1, t1, t0 addi t2, t2, 8 addi t3, t3, -2 bnez t3, loop
Press the F3 or Run | Assembler. The program will turn into machine code, the instructions of the RISC-V processor:
Now press F7 or Run | Step. The program will go one step, one instruction, and load constant 1 into register t0 / register 5 (highlighted in green). After that, it will turn to the following instruction (highlighted in yellow):
You can take a few more steps and see how the program starts writing numbers to memory (below, highlighted in blue):
Now click on F5 or Run | Go. The program will be executed to the end – it will write 64 Fibonacci numbers into memory. In a real processor, the program will continue further (jumping on instructions in memory after our code), but RARS notices the end and stops:
That’s all. Write your own 2 + 2 addition program, attend a seminar on Saturday and you can consider yourself an assembler programmer, and on the most hype architecture of our time. Nikita Polyakov, in addition to simple arithmetic operations, loops and branches, is also going to talk about the mechanism of calling functions through the stack (write the Heinoy Towers in assembler if you understand this), as well as how various constructions of the C language are translated into assembler.
And in one of the next lessons, another designer of the Russian RISC-V core from Syntacore, Stanislav Zhelnio, will show you how to design your own version of a microprocessor of a subset of the RISC-V architecture and implement it in hardware on a reconfigurable logic board FPGA / FPGA.
If you haven’t heard anything about the Skolkovo School of Digital Circuit Synthesis, here is website and registration… There is also a link to the first lesson on verlog, if you missed it.