SSDs. The internal structure and principles of their construction

8 min

Our customers are often interested in the internal design of solid state drives. What determines the reliability of drives? Why is it impossible to store important data on flash drives and are there reliable flash drives? Why are multi-core processors placed in SSD controllers? Why do flash drives write large volumes quickly, and small volumes write slowly? Many questions require a long immersion in the topic, and some disappear by themselves after a small educational program on the internal structure of solid-state drives, which will be discussed.


A USB flash drive, a microSD / SD memory card, and an SSD drive are, at first glance, different devices, although they are actually “close relatives”. All three types of devices are based on solid state drives based on NAND flash memory. A funny fact, commonly referred to as “SSD disks” in the home, are not disks in the literal sense. The name “disk” is historically inherited from hard disk drives (HDD).

Despite the difference in application, the architecture of all SSDs in general looks the same.

Solid state drives include:

  • Controller – the main element of a solid state drive that performs the functions of reading, writing, data integrity control and correcting bit errors that occur in the structure of NAND flash memory. On the one hand, the controller connects to the host via an external SATA / USB / SD / PCIe interface, and on the other hand, to the NAND flash chips through the ONFI / Toggle connection interface
  • NAND flash memory – an array of microcircuits forming the amount of memory of the drive

To understand the tasks performed by the controller, you need to have a basic understanding of the organization of NAND flash memory. NAND flash memory chips are quite specific in use, starting from the connection interface and ending with the reliability of information storage.

NAND flash memory

NAND flash memory chip – a storage for user information (photos, films, documents, system files of the operating system, etc.).

Let us dwell on the issues of the data access interface and the problems of information security in NAND flash memory that are relevant for SSDs.

The NAND flash chip can be compared to an archive of paper documents. Like how papers are stored in the archive, electronic documents are also stored in the memory of microchips.


Critical functions of any data storage systems and archive are:

  • Data storage – the archive must have conditions ensuring the safety of papers
  • Access to the information – the librarian should be able to work with the necessary document, otherwise the archive is useless

Storage conditions ensuring the safety of papers (temperature, humidity, protection from rodents) determine the integrity of the data, and the presence of an entrance door, spans between shelves provides access to papers. By analogy, we can say that each bit of data in the flash memory is stored as a charge in the floating gate of the transistor (cell). To record a bit of information in a cell, a certain charge level is programmed.

However, the flash storage system has the following features:

  1. The charge from the shutter can “leak” over time, which sooner or later will lead to data changes. For example, how ink on archival papers fades or spreads over time, turning into illegible spots. The longer the data is stored, the less likely it is to read it later.
  2. After the same circuits record the same logical charge level in different cells, due to the technological spread of the transistor parameters, it will be possible to read charge values ​​of different magnitude from there. (Paper may have different properties of ink absorption and spreading. Small text written with a felt-tip pen cannot be read on every paper.)
  3. Charge recording and reading circuits are also not ideal and have a technological spread of programming voltage levels and reading thresholds of logical levels. (It looks like different librarians can make out text written by different authors in different ways on paper, because everyone has different handwriting.)


The purpose of the technology for developing memory chips is to create flash memory with a maximum quality / price ratio. For storing data in drives
NAND flash memory is a very worthy solution in this ratio, as evidenced by the growth of the drive market. But the quality / price ratio is not the same as quality. The chip cost directly depends on the chip area. Therefore, flash memory manufacturers are constantly striving to increase the density of data storage in memory chips. An increase in the density of memory cells is achieved by reducing the size of the cells themselves, and by combining the write circuits and reading the cell charges. Moreover, the second, in turn, creates some difficulties in accessing stored data.

Access Interface Concepts and NAND Flash Access Rules:

  • Block. The entire volume of the chip is divided into blocks. The block size is about a few megabytes. (For example, in the archive, this is a book or notebook in binding with stitched sheets)
  • Erase a block. A block can be erased, and each bit of information in it will be set to “1”. You cannot erase only part of a block. (For example, a book can be thrown out, but you cannot tear a sheet from a book without violating the integrity of the book)
  • Page. The block is divided into pages about tens of kilobytes in size. (For example, books and notebooks also have pages)
  • Programming the page. In NAND flash memory, data of the whole page can be written (programmed) at the same time, bits are set during programming to the values ​​“0” or “1”. (For example, blank pages of a book or notebook can be filled in with information only once)
  • The procedure for programming pages. Pages within the block must be programmed strictly in ascending order of their numbers. (For example, sequential recording of information in a book or notebook)
  • Rewrite order. Each page can only be programmed once. To re-program the page, you must erase the entire block. (For example, if you need to replace the page in an already finished edition of a book, you will have to reprint the entire book and re-make the binding)

The above features of NAND flash memory look quite harmless at first glance, but many questions arise when you first try to overwrite part of the data (for example, one sector). The tasks of writing and reading directly to NAND flash memory are solved by the controller.


The controller provides a connection to the host, and, in fact, appears to be a drive. In general, the architecture of any controller of any drive looks typical: there are hardware interface blocks for exchanging data with the host (EXT_IF) and NAND-memory (FLASH_IF). Between the blocks of interfaces, there is a mandatory buffer memory (MEM_BUF), designed for online caching of data and smoothing of the write / read data stream. In USB storage controllers, the buffer memory is tens of kilobytes and is located directly in the controller itself. High-performance systems, such as SSDs, use external memory chips. Data between the interface units and the buffer memory is transmitted without the direct involvement of the processor via direct memory access (DMA) channels. The participation of the processor in data transmission is to configure DMA channels and synchronize the operation of blocks.


Any of the plug-in drives is a “block device”. A block device is a device in which data is stored as a sequential chain of logical blocks, access to which is possible at Logical Block Address (LBA). Most devices support a block size of 512 bytes, which is called the “sector”. A sector is the minimum discrete information that can be overwritten on a block device. That is, to replace one byte, the host must transfer the entire sector to the storage device.

For programmers working with drives at the physical level (writing / reading to physical addresses), it is quite obvious that writing and reading from one sector should not affect the data of other sectors in any way. It is also obvious to the user of the block device, but NAND flash memory, as mentioned earlier, does not provide such an opportunity. In order to replace one sector in the NAND memory array, it is necessary to overwrite the entire NAND block of flash memory, the size of which is megabytes. This method of solving the problem is extremely inefficient, as it leads to an unacceptable decrease in the speed of writing to NAND flash memory relative to its potential capabilities. Moreover, since the operating system often writes to the same device addresses (for example, FAT records), the NAND blocks of flash memory will quickly become unusable due to the limited erasure resource. To increase the speed of writing / reading data and extend the life of the NAND flash memory, more sophisticated addressing methods are used that translate the logical addresses (LBA) of the drive into the physical addresses of the NAND flash memory. The NAND flash address translation algorithm in foreign literature is called Flash translation layer (FTL). If you look at the description of SSD controllers (for example, companies Marvell), then you can see that the controller includes up to 4 processor cores. Such a high-performance system in the SSD is necessary primarily for calculating broadcast addresses.

FTL, logical and physical addressing

There is no single universal FTL algorithm that satisfies all user requests, which include:

  • write / read speed of data at serial addresses
  • write / read speed of data at random addresses
  • drive life
  • reliable data storage
  • amount and type of memory used

FTL algorithms can differ for different types of drives (SD / USB / SSD), and for one type. For example, there is a separation of SSDs by purpose: for servers, for caching in a personal computer (PC), for laptops, for desktop PCs. Moreover, for each application, there are priorities in the requirements and their own FTL implementation options. Each FTL option is a compromise of parameters, taking into account the priorities of a particular drive application.

The essence of FTL is the conversion of device logical addresses to physical NAND flash addresses.


Each logical LBA is assigned a memory area in NAND. This is called the Logical Unit Number Table (LUN table). To rewrite a logical block, the data of a free physical block is erased, after which it is replaced in the LUN table, which creates the appearance of rewriting for the user. The size of the LUN table depends on the size of the logical blocks (it is not advisable to have large amounts of memory in all devices). There are two fundamentally different approaches to FTL implementation: block addressing and page addressing.

Block addressing

In block addressing, the size of the logical block corresponds to the size of the physical block. In turn, in the LUN table array with an index equal to the address of the logical block, the value corresponding to the address of the physical block is indicated. To change part of a block, you must rewrite the entire block.

The advantage of block addressing is the small size of the LUN table, which is important for devices with a small amount of RAM, such as a USB flash drive or microSD memory card. The disadvantage is that the block size is quite large (about megabytes), and to overwrite small amounts of data (for example, 512 bytes), you have to rewrite the entire block.

Page Addressing

In page addressing, the addresses of physical pages are stored in the LUN table. The size of the logical unit is about tens of kilobytes.

The advantage of paging is the high speed of data overwriting, both sequentially and randomly. The disadvantage is the large size of the LUN table. Therefore, most SSDs include a memory chip with a capacity of more than 100 MB.

In practice, mainly used hybrid algorithms that combine both addressing options. For example, in compact drives (USB flash drive, SD memory card), the bulk of the volume is addressed by the block method, while the part of the volume that is often accessed is addressed page by page.

This is the structure and principles of operation of NAND flash drives. A large number of scientific articles have been written about FTL addressing methods and many solutions have been patented. Controller manufacturers are constantly working on improving software even after the product enters the market. In general, the software is an integral part of the controller and its description deserves a separate article.


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