RnD cycle of modern SoCs, physical implementation for FPGA and ASIC, review of prototyping systems

On October 26 at 11:00, the first autumn meeting of the FPGA-Systems community in St. Petersburg, organized jointly with YADRO, starts. Engineers will share their experience and talk about ASIC development, physical design, the new AG32 chip from AG micro and much more. The meetup is interesting not only because of its rich program, but also because of its open demo zone with the best practices of engineers.

Registerto get to the meetup in St. Petersburg or get a link to the broadcast on VK, YouTube or Rutube, where you can ask questions to the speakers.

What's in the program

Development of modern ASIC/SoC on behalf of a physical designer, or backend kitchen

Ilya Peplov

Physical synthesis engineer (backend), YADRO

You will find an overview of the RnD cycle of modern SoCs with an emphasis on the topology design stage. What topics will I cover in the report:

• The main steps of the physical synthesis route.

• Organization of work inside backend-teams.

• Interesting features of modern chips.

• The challenges that topologists face are, for example, when RTL-freeze happens a month before the takeout.

Physical Design: FPGA vs ASIC

Alexander Vlasov

Lead SoC development engineer in the physical implementation team, YADRO

The quality of a project's logical design depends on its physical implementation—the hardware that will execute the loaded program. Now FPGA and ASIC are popular options for such implementation. All the “pros et cons” of these approaches are already known, the criteria for when an FPGA project should become an ASIC are clear.

In the report I will talk about the difficulties of transitioning from the FPGA implementation of the original RTL to the ASIC paradigm:

• Where does the physical implementation for FPGA and ASIC begin?

• Similarities and fundamental differences between the stages.

• What is good in FPGA and very difficult in ASIC.

How FPGA is used in scientific environment

Alexander Boykov

Junior Researcher, Joint Institute for Nuclear Research

This is a report on technologies that the scientific community has developed and improved. Let's look at examples of the use of these technologies in experimental setups and special tools for solving problems that arise when working with FPGAs.

Running Embedded Linux on Hard and Soft CPU Xilinx Zynq

Pavel Pankratov

Leading software engineer of the department for designing new generations of technology stack, YADRO

Yana Bulina

Software engineer of the design department for new generations of technology stack, YADRO

The everyday tasks of the Embedded world are sometimes not so trivial and well mastered. Let's talk about running two OSes in parallel on an FPGA with a processor subsystem and how to be a technology pioneer. In the report we:

• Let's look at the necessary blocks of programmable logic to run the OS.

• Let's talk about the differences between approaches for FPGAs with and without a built-in Hard CPU.

• Let's go over the minimum required components, tools for building Embedded Linux and their limitations.

• Let's look at Devicetree and bootable media layout.

• Let's solve the riddle: “How many bootloaders do you need to run two operating systems?”

Arduino family board based on RISС-V SoC with built-in programmable logic

Evgeniy Kuklov

Device Development Engineer

Alexander Syrov

Business Development Manager at GetChips

During the talk we will introduce you to the new generation of microcontrollers. Together, let's look at the AG32 SoC from AG micro, which combines the power of RISC-V, the flexibility of FPGAs and peripherals in STM32-compatible packages. In the report we:

• Let's explore the possibilities of tight integration between the processor, FPGA and peripherals.

• Let's review the tools for programming and debugging the AG32.

• Let's evaluate how the new features expand the capabilities of developers.

Experience in developing an ASIC prototyping system

Alexander Ogurtsov

Head of FPGA Prototyping Department at YADRO

I’ll briefly tell you about a flexible and scalable system for FPGA prototypes, which allows you to reuse the developed architecture for all our projects. In the report, I will compare approaches to ASIC prototyping and talk about the advantages and disadvantages of our FPGA test bench architecture in relation to prototyping systems on the global market.

PyUVM for FPGA software verification: a guide for dummies

Venus Farakshina

Verifier at JSC “TsKBA”

If you are just starting to get acquainted with FPGA verification, pay attention to PyUVM – it is a Python library that allows you to create test environments based on the UVM methodology. This makes verification more accessible to beginners.

What will be in the report:

• Fundamentals of the UVM methodology and its application to verification.

• Step-by-step setup of a verification environment using PyUVM.

• Examples of writing tests, modeling and analyzing results.

• Review of common errors and methods for solving them in the verification process.

Where and when do we meet?

October 26, Saturday. The conference starts at 11:00, gathering of guests starts at 10:30.

In St. Petersburg: Petrocongress center, Chkalovskaya metro station. Entrance by registration — you need it to secure your place in the hall.

Online: we will send a link to the broadcast on VK, YouTube or Rutube after registration on the website.