Reverse engineering of the old OR chip
Not so long ago I received a photo of the crystal of the mysterious OQ100 circuit  from
… I analyzed it and found it to be a logic chip implemented in a fast ECL (emitter coupled logic) circuit and probably dated back to the early 1970s. The chip contains three logic gates, two with 2 inputs and one with 4 inputs. Each element has non-inverted and inverted outputs, acting as OR and NOR gates. This article summarizes my research. (I recently also analyzed
, another chip from this series.)
Photo of the crystal of the Philips QC100 microcircuit. Photo courtesy ofEvilMonkeyDesignz…
The photo above shows the chip under a microscope. Most of the silicon in the image is bright pink. Areas of silicon with different doping have green or yellowish tints and form the transistors and resistors of the microcircuit. The patchy areas are a metal layer on top of the silicon that binds the components together. Black wires around the edges connect the chip to the outside pins.
Transistors are the key components of a microcircuit. This chip uses a type called NPN transistors. The photo below shows how the transistor looks on the microcircuit. Below the photograph is a cross-sectional drawing showing the approximate structure. In fact, the transistor is more complex than a simple NPN sandwich from books, but if you look closely at the figure under the letter E, you can see the NPN layers that form the transistor. The emitter contact (E) is connected to N + silicon. Below is the P layer, connected to the base pin (B). And below it is the N layer, connected to the collector ©.
NPN transistor structure. Above: transistor on chip. Bottom: sectional diagram.
The chip also uses multiple PNP transistors. While it might seem like a PNP transistor is just an inverted NPN transistor, it actually has a different structure, based not on the vertical arrangement of the regions, but on the horizontal one. The collector and base form concentric square rings around the emitter. The base contact is not directly connected to the base area. Instead, the contact is at a distance and the base signal travels down through layer N.
PNP transistor structure. Above: transistor on chip. Bottom: sectional diagram.
There is another complication with PNP transistors on this chip. The collector is split, so the transistor has two collectors. Moreover, one of the collectors is connected directly to the base. In the photo above, you can see how the collector area is vertically split, so there is one collector on the left and one on the right connected to the base. This design may sound fancy, but it is quite common in integrated circuits. Its purpose is to build a current mirror in which both collectors pass the same current.
The other key components of this IC are resistors. The photo below shows two resistors on a chip. The resistors consist of strips of silicon P, which has a higher resistance and is shown in pink in the photo. Each end of the resistor is connected to a metal layer; the metal in the middle connects the two resistors in series. (The metal path also passes through the resistor, but does not connect to it.) The longer and narrower the resistor, the higher the resistance, so these resistors have a relatively high resistance. … Directly on the diagram, the resistors are quite large and inaccurate.
Two resistors on a chip.
The components have been recognized, now you can proceed to reverse engineering. But before describing the complete circuit, I will explain how ECL (Emitter-Linked Logic) works … The diagram below shows a differential or long tail pair that amplifies the difference between the two inputs. (This circuit is also common in analog circuits, forming the basis of an operational amplifier.) The basic idea is that the current sink (circle at the bottom) generates a fixed current
… This current is split between the left path (
) and the right path (
). If the transistor on the left has a higher input voltage than the transistor on the right, most of the current will flow to the left path. But if the transistor on the right has a higher input, most of the current will flow on the right path. This circuit amplifies the voltage difference: even a small difference between the two inputs will switch most of the current from one side to the other.
Diagram of a simple differential pair circuit. The current sink transmits a fixed current I through the differential pair. If the two inputs are equal, the current is divided equally between the two legs. Otherwise, most of the current will flow on the branch with the higher input voltage.
To turn a pair into an OR gate, multiple transistors can be placed on the left. If any of the inputs are high, the current will switch to the left, otherwise the current will switch to the right. Since the current pulls this side down to a low level, the left leg will be the NOR output and the right leg will be the OR output. (With ECL, you get inverted and direct outputs “for free.”) The diagram below shows an implementation of a single gate; it is a valve with two inputs. The second differential pair is used to buffer and amplify the output signals. The current sink circuit is discussed in the footnote …
Scheme of one logical element.
The diagram below shows an on-chip implementation of a four-input gate. Most of the area is occupied by a current sink and corresponding resistors. NPN and PNP transistors are relatively compact, but resistors take up a lot of space. At the bottom, four input transistors implement the OR function along with a reference transistor on the other branch. The output transistors are larger so they can supply more current.
One logical element with marked functional blocks.
The diagram below shows the location of three logic gates on a chip. (The item described above is on the right.) The voltage divider resistors provide the voltage reference for the current sources.
Crystal with marked main functional blocks.
The diagram below shows how the circuitry of the microcircuit corresponds to its 16 pins. Three logical OR elements are represented by OR symbols; the gate on the right has four entrances. Each valve has a non-inverted output and an inverted output, which is indicated by a bubble. I do not know what voltage the microcircuit accepts, so I marked the power pins with + and – signs.
Putting it all together, the diagram below shows how the IC schematic maps to its 16 pins. The three OR elements are represented by OR symbols; the element on the right has four entrances. Each valve has a non-inverted output and an inverted output, which is indicated by a bubble. I don’t know what voltage the chip accepts, so I labeled the power pins + and -.
The figure below shows how the circuit relates to the 16 pins. The three OR gates are represented by corresponding symbols; each element has 4 entrances. The elements also have a non-inverted and an inverted output, indicated by a circle. I do not know how the voltage is received by the chip, so I marked the power pins + and -.
Pinout of the microcircuit.
- The reader explained that Philips used the OQ designation for their custom integrated circuits. This might explain why I was unable to find these chips in the reference.
- The resistance of the resistor is proportional to the length divided by the width. To understand this, notice that the double-length region is equivalent to two resistors in series, so its resistance is double. The double-wide area is similar to two resistors in parallel, so its resistance is half the size.
- The logic on this microcircuit has several differences from the standard ECL elements. A typical ECL element has inputs on one leg and a voltage reference connected to a transistor on the other leg. Thus, an input above the reference voltage is logic 1, and an input below the reference voltage is logic 0. However, here the output of the first branch is fed as an input to the second branch. If the input is high, it pulls that output low, overlapping the other branch. Conversely, if the input is low, the output goes high, turning on the second branch.
I don’t know what caused this design. This is a bit like NTL (Non-Threshold Logic) in that there is no threshold set by the reference voltage. Perhaps the circuit implements a Schmitt trigger, a circuit with hysteresis, where when the circuit is turned on, the input must go much lower to turn it off.
The second difference between this schema and a typical ECL element is the output buffer. ECL elements typically use an emitter follower rather than a second differential pair.
- I will just briefly describe the current sink circuit shown below. The two large resistors form a voltage divider that creates a voltage reference halfway between the two supply voltages (possibly 0 volts). Due to the behavior of the transistors VBE will be one diode drop (~ 0.7 V). The rest of the circuit generates the “correct” current through the lower right resistor to achieve this voltage drop. On the chip, the two PNP transistors at the top represent one transistor with two collectors. They implement a current mirror in which the current through the right transistor is the same as the current through the left transistor.