The IBM company seems to have managed to achieve what other corporations have not yet succeeded in developing a processor using a 2nm process technology. And not just develop, but demonstrate test samples of these processors. According to the company, “50 billion transistors have been placed on a chip the size of a fingernail.”
Despite the obvious success, soon the market will not receive new chips – they will arrive no earlier than 2024, and then only if IBM does not have unforeseen problems. It is worth noting that the test samples of the chips were produced not by the TSMC factory, but by IBM’s own laboratory located in Albany, USA. Samples were made on 300 mm plates.
2nm is better than 7nm
Despite the fact that 5nm processors are already in full swing, IBM chose to compare the capabilities of its chips with processors manufactured in 7nm topology. According to representatives of IBM, the new product is 75% more productive at the same level of power consumption. If the performance of new processors is artificially slowed down to 7 nm chips, then the power consumption will decrease by 45%.
By the way, back to the mention of the “nail”. Anandtech journalists asked the company for clarification, asking for a more objective assessment of the size of the chip. After all, nails can be different – different people have their area from 50 to 250 mm2…
It turned out that the average nail plate area, according to the company, is about 150 mm2, so the original description is true. The result is 333 million transistors per square millimeter. Below is a comparison table:
|Peak Quoted Transistor Densities (MTr / mm2)|
|16nm / 14nm||28.88||44.67||33.32|
There is one complication here – manufacturers often indicate the peak density in certain areas of the chip. In fact, the figure may be half as much due to problems with energy consumption and a possible rise in temperature.
Now IBM is trying to optimize its chips so that commercial samples outperform processors made in other technical processes in all respects.
Images published by IBM show a three-stack GAA (Gate-All-Around) transistor design. Its cell height is 75 nm, its width is 40 nm, and the thickness of the inner layers is 5 nm. The pitch of the polysilicon gate with contact is 44 nm and the gate length is 12 nm.
Where will 2nm chips be used?
According to the manufacturer, first of all, they will be useful for the development of artificial intelligence technologies, as well as in edge computing. But these processors will come in handy in many other areas as well. The company has already announced that it will use them in IBM Power Systems servers and Z-series mainframes.
They can also be used in mobile devices, making the latter much more productive while consuming less energy. Laptops are another niche for new items. True, the company does not yet give forecasts for the autonomy of either mobile devices or laptops with new chips.