How the first x86 hybrid processor works

Chart of a computational chip in the Intel Lakefield processor: one Core (Sunny Cove) core and four Atom (Tremont) cores

Ten years ago, ARM introduced the heterogeneous architecture of multi-core processors big.LITTLE from different cores: some were high-performance and others were energy-efficient. Such a hybrid system allowed to significantly reduce the power consumption of the CPU during the background operation of applications (that is, almost always). The consequence was an increase in the operating time of the devices.

In 2019, heterogeneous architecture was finally first introduced by Intel in x86 processors. In 2020, two Lakefield processors with a 1 + 4 configuration will enter the market (one Core core and four Atom cores), writes AnandTech.

Lakefield Processors

Intel Lakefield Processors
i5-L16G71 + 414003000180064 EU50042677 watts
i3-L13G41 + 48002800130048 EU50042677 watts

Comparison with other CPUs

Comparison of Lakefield with other processors
SD 7c
Goldmont +Kryo
Kernel Configuration1 + 42 + 02 + 00 + 40 + 8
TDP7 watts9 watts5 watts6 watts~ 7 W
4 x TNT
2 x SNC2 x SKL4 x GMN +8 x Kryo
GPUGen 11
64 EU
0.5 GHz
Gen 11
32 EU
0.9 GHz
Gen 9
24 EU
0.9 GHz
Gen 9
18 EU
750 MHz
WifiWi-Fi 6 *Wi-Fi 5 *Wi-Fi 6
ModemCat15 / 13


The processors themselves have not yet appeared in the public domain, so it remains to focus only on Intel benchmarks. The company gives only two comparisons: with Amber Lake-Y, i.e. 5W i7-8500Y, as well as i5-L16G7 with itself in 1 + 4 and 0 + 4 modes (in fact, a comparison with the Atom four-core design).

According to the first point in comparison with Amber Lake-Y:

  • + 12% performance of one thread according to SPEC2006 (3.0 GHz for Lakefield versus 4.2 GHz for Amber Lake-Y)
  • + 70% 3DMark11 graphics performance compared to HD615 (24 EU, Gen 9.5 at 1.05 GHz, 2×4 GB LPDDR3-1866) versus HD (64 EU, Gen11 at 500 MHz, 2×4 GB LPDDR4X-4267)
  • + 24% watts energy efficiency on WebXPRT 3
  • + 100% AI loading on graphics, ResNet50 128 package on OpenVINO

1 + 4 mode compared to 0 + 4 gives an increase of 33% in web productivity and + 17% in energy efficiency. In fact, in most tasks, Lakefield will operate as a quad-core Atom.

Factory-tested Intel Lakefield processors for durability. Photo: Anandtech

Why does a processor need a “large” core? It is needed to handle the highest priority interrupts when it is necessary to ensure the minimum delay: pressing the screen, typing on the keyboard, and the like. This ensures the responsiveness of the device even at times of maximum load of the remaining four cores.

How are heterogeneous CPUs arranged?

Lakefield combines on one chip one large Core core and four small Atom cores. In regular reviews, these x86 processors may be called “five-core” and are usually written as 1 + 4.

Processor size 12 * 12 mm

Intel’s goal is to combine the benefits of an energy-efficient Atom core with a more energy-consuming, but also more “gluttonous” Core core. The result is an intermediate processor between the design of “all Atom cores” 0 + 4 and “all Core cores” 4 + 0.

The easiest way to compare Lakefield with the old four-core Atom processors, where they added a large core. A cluster of four smaller Atom cores takes care of large parallel loads, while a large core responds when a user loads an application or touches a screen, or scrolls a page in a browser.

Hybrid architecture is already used in ARM processors and even on Windows operating systems, like Qualcomm Snapdragon processors on laptops such as Lenovo Yoga (4 + 4 design). Qualcomm had to work a lot with Microsoft to develop an appropriate scheduler that can manage workloads between different processor core designs.

Design visualization of different heterogeneous CPU architectures (no scale)

The main difference between Qualcomm and Intel is software support: Qualcomm processors execute ARM instructions, while Intel processors execute x86 instructions. Most Windows programs are built for x86 instructions, which limits Qualcomm’s performance in the traditional notebook market. Qualcomm’s design actually allows for “x86 translation,” but the scope is limited and there is a penalty for performance. However, work in this direction continues.

3D layout Foveros

The whole chip fits in a 12 * 12 mm case2so that real silicon is much smaller: the area of ​​the bottom chip is 92 mm2and the top 82 mm2

The overall design of the CPU with the Foveros 3D layout is shown in the diagram above. As you can see, the main computing chip is located on top, and the base is on the bottom.

The upper 13-layer is manufactured using the 10 nm manufacturing process, and the lower 10-layer is manufactured using the 22 FFL manufacturing process.

Computing Chip

As indicated in the table, the microcircuits are different from each other and are produced according to different process technology.

Graphics Gen 11 occupies 37% of the area, the configuration as in the Ice Lake processors. On top is the core of Sunny Cove, just like in Ice Lake. Intel engineers said they physically deleted the AVX-512 registers from the chip, although they are visible in the photograph.

Below are four Tremont Atom cores, with a total area of ​​about one single Sunny Cove core.

The contents of the computing chip:

  • 1 x Sunny Cove core with 512 KiB L2 cache
  • 4 x Tremont Atom cores, 1536 KiB L2 cache on all
  • 4 MB last level cache
  • Interconnects uncore and ring
  • 64 Computing Gen11 Graphics Unit
  • Graphic engines Gen11, 2 x DP 1.4, 2x DPHY 1.2,
  • Gen11 media core supporting 4K video at 60 fps and 8K at 30 fps
  • Image Processing Unit Image Processing Unit (IPU) v5.5, supports up to six 16 MP cameras
  • JTAG, Debug, SVID, P-Unit, etc.
  • LPDDR4X-4267 memory controller

Power diagram and TSV signal point design (through silicon vias)

Base chip

Photo of the bottom base chip

The base chip is much simpler and is manufactured using the 22FFL process technology, which is an optimized version of the 14-nanometer process technology with less stringent restrictions, so Intel can produce these chips without any problems in almost any amount. The main difficulty is the connection between the two chips (die-to-die).

Forevos die-to-die interconnect (FDI)

The contents of the base chip:

  • Audio codec
  • USB 2.0, USB 3.2 Gen x
  • UFS 3.x
  • PCIe Gen 3.0
  • Touch hub to support continuous activity (always-on)
  • I3C, SDIO, CSE, SPI / I2C

The first laptops and tablets

A number of Lakefield-based laptops and tablets are ready for release. Among the first devices …

Galaxy Book S laptop (it is also available on Qualcomm Snapdragon 8cx processors with similar specifications), should appear on sale in July 2020

Lenovo ThinkPad X1 Fold foldable tablet laptop with crazy price of $ 2,499 for 1 TB version

and the Microsoft Surface Book Neo tablet, which will be released closer to winter.

Future lakefield

Even if this version of Lakefield doesn’t look too good in benchmarks, this is a big step for Intel. Hybrid designs and multi-level bonding between substrates are presented in Intel’s development plans. It all depends on how Intel is willing to experiment and how well it can implement engineering ideas. There has been discussion that Intel may be considering a hybrid 8 + 8 processor design in the future. Nothing is known about this, but the Ponte Vecchio with a multi-level backing is definitely planned for the end of 2021.

Motherboard size for Lakefield (30 * 123 mm) compared to previous generation motherboards

Perhaps some innovative Intel processors will not be released for desktop computers, but, for example, for cars or 5G networks. As for Lakefield, in fact these are relatively low-performance CPUs that will be installed on laptops and tablets, like Atom processors. We can say in advance that competing in this segment will not be easy, especially with AMD mobile processors and ARM processors such as Snapdragon. But the more competition, the better the customers.

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