“FPGA inside out” – a cartoon about CRC calculation and parallel CRC

Friends came up with the idea to create several educational cartoons about FPGA, which would show not only the blinking of the LEDs on the board while manipulating it, but also the visualization of the logic of the circuit in real time.

For the first video, a CRC calculator (cycle redundancy check) based on a feedback shift register was chosen as an experimental scheme.

It is easier to show what experiments the circuit undergoes during the demonstration than to “describe with a pen” – so let’s watch the video:

As a result, as we saw from a simple shift register, you can “untwist the story” explaining, in addition to the shift register itself, such concepts as: the circuit and the principle of calculating CRC, converting the shift register into a parallel circuit (parallel CRC) along the way showing signal propagation patterns through the combinational and sequential logic of the circuit .

For today, I plan to make several videos with visualization of other concepts of hardware design. Interesting candidates for experiments: stream interfaces, pipelines, FIFOs, timings (STA), etc. In order for the cartoons to be not only pleasant to watch but also useful, then (if possible) we will accompany them with Verilog code so that the viewer can repeat the experiments on their own on the debug board at hand.

In the next article, I think to talk about the very principle of creating such videos and about the program for creating them. The program written in python, along with the manual, will soon be posted on Github – maybe it will be useful to someone to create such videos, and maybe the community will even have a desire to improve or supplement it. And there will definitely be room for additions and improvements.

On this, thank you for your attention – criticism, suggestions and comments are more than welcome.

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