Found a bug in the American education system

Found an interesting bug in the American education system:

Many students have “did a course project on the Tomasulo algorithm, out-of-order superscalar, multi-threaded processor, etc” in their resumes.

To this I ask: “Fine, let’s take two processor cores – one with a static pipeline, and the other with a dynamic one, as in your course book. How much more productive will your processor be?”

To this they answer “the processor will be more productive because” – and start poking around in the details of the dependencies between instructions.

To this I wave my hands and say “stop-stop-stop. I did not ask you to explain to me what RaW (read-after-write), WaR and WaW dependencies are. I did not ask you at all “why?” I asked you “how much?” I asked you to roughly estimate the benefits of your development.

Here you, together with other students, under the guidance of a professor, designed a processor, did a rather complex, advanced optimization. Now let’s take the verilog you wrote, run it in the simulator and run a benchmark through it, say Dhrystone or CoreMark. Let’s say that a processor with a static pipeline had some benchmark iterations in a hundred thousand cycles. How many cycles will the same benchmark take on your processor – in a hundred cycles or in a million? Or for something in the middle? How much are you buying with your optimization – 1%, 10%, 100%? What is the price in terms of logic? Maybe the clocks will change a little, but the maximum clock frequency will increase? How much?”

And can you imagine what they say to me? “We didn’t run benchmarks.”

They have benchmarks in their textbooks – I don’t think so, but I know, since all their textbooks are on my shelf. This looks to me purely like bad teacher work: teachers should:

  1. Give a bird’s eye view of how many different optimizations are buying and at what cost.

  2. Reinforce this knowledge by measuring benchmarks and static timing analysis during course projects. Also – if the university has access to Synopsys PTPX or Cadence Joules, then measure dynamic power consumption. But if not, you can measure clocks and STA with free tools – Icarus Verilog and Open Lane.

However, there are more problems in Russia and Ukraine than in American universities: I was told several years ago that MIPT taught pipeline processors using the cycle-accurate model in C++, without measuring static timing analysis for different microarchitecture options. Well, it’s like teaching electricity without magnetism. Though it’s been a while since then and I hope they fixed it.

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