DDR5 Memory Specs Released
DDR5: four memory chips per bank, the fifth for on-die ECC check
Marking an important milestone in the development of computer memory, JEDEC has released final specification the next major standard for DDR5 SDRAM. The latest iteration of the DDR4 standard has been the mainstay of PC and server development since the late 90’s. DDR5 once again expands memory capabilities by doubling both peak speed and memory capacity. Iron on the new standard is expected in 2021, with implementation starting at the server level and then leaking to client PCs and other devices.
DDR5 release originally planned for 2018. Today’s release of the DDR5 specs is slightly behind the original JEDEC schedule, but that doesn’t detract from its importance. As with every previous DDR iteration, the focus for DDR5 is again focused on improving memory density as well as speed. JEDEC aims to double both, setting a maximum memory speed of at least 6.4 Gbps, while the capacity of a single full packed LRDIMM can reach 2 TB.
| Generation JEDEC DDR | ||||||
| DDR5 | DDR4 | DDR3 | LPDDR5 | |||
| Max. density of one core | 64 Gbps | 16 Gbps | 4 Gbps | 32 Gbps | ||
| Max. UDIMM size | 128 GB | 32 GB | 8 GB | N / a | ||
| Max. transmission speed | 6.4 Gbps | 3.2 Gbps | 1.6 Gbps | 6.4 Gbps | ||
| Kaanalov | 2 | 1 | 1 | 1 | ||
| Width (Non-ECC) | 64-bit (2×32) | 64-bit | 64-bit | 16-bit | ||
| Banks (Per Group) |
4 | 4 | 8 | sixteen | ||
| Bank groups | 8/4 | 4/2 | 1 | 4 | ||
| Package length | BL16 | BL8 | BL8 | BL16 | ||
| Voltage (Vdd) | 1.1V | 1.2V | 1.5 V | 1.05 V | ||
| Vddq | 1.1V | 1.2V | 1.5 V | 0.5V | ||
Designed for several years (or decades), DDR5 will allow the use of individual memory chips up to 64 Gbps, which is 4 times the maximum density of 16 Gb DDR4. Combined with stacking that allows up to 8 cores (dies) to be stacked on a single chip, a 40-cell LRDIMM can achieve an effective memory capacity of 2TB or 128GB for conventional DIMM designs.
But the amount of memory will grow gradually, but the speed will increase instantly. DDR5 will launch at 4.8Gbps, which is about 50% faster than the official 3.2Gbps DDR4 maximum speed. And in subsequent years, the current version of the specification allows for data rates up to 6.4 Gbps. With the technological development, SK Hynix can actually achieve its target DDR5-8400 in this decade.
At the heart of these speed targets are changes in both the DIMM and the memory bus to feed and transport a lot of data per clock. Since the clock frequency is stuck at several hundred megahertz and it is not yet possible to increase it, it is necessary to increase parallelism (the same thing happens in the CPU, where more cores are added to the chip).
As with other standards such as LPDDR4 and GDDR6, one DIMM is split into two channels. Instead of one 64-bit data channel per DIMM, DDR5 offers two independent 32-bit data channels (or 40-bit with ECC verification). Meanwhile, the packet length for each channel is doubled from 8 bytes (BL8) to 16 bytes (BL16), so each channel will deliver 64 bytes per operation. Thus, a DDR5 DIMM at the same core speed will perform two 64-byte operations in the time it takes a DDR4 DIMM to complete one, doubling the effective bandwidth.
Besides changing memory banks, JEDEC introduced a slightly modified bus, although it works with tighter tolerances.
A key driving force here is the introduction of decision feedback equalization (DFE). At a very high level, DFE is a means of reducing intersymbol noise by using feedback from the memory bus receiver to provide better alignment. Better alignment, in turn, allows for a cleaner signal for the bus to increase the transmission speed.
Along with changing core density and memory speed, DDR5 also improves operating voltages. According to the specs, DDR5 will operate at a Vdd of 1.1V, compared to 1.2V for DDR4. Like previous updates, this should slightly improve memory power efficiency. In addition, the modules now have built-in voltage regulators.
DDR5 DIMM memory still has 288 pins, but the pinout is different.
This is reminiscent of the transition from DDR2 to DDR3, where the number of contacts also remained the same: 240 contacts.
But of course, DDR5 cannot be used in old sockets, even if it is inserted there.
JEDEC sets a standard that its members can use. Major memory manufacturers that have been involved in the DDR5 development process from the beginning have already developed DIMM prototypes and are now considering bringing the first commercial products to market. For example, SK Hynix released a DDR5 prototype back in November 2019.
The first DDR5 modules and motherboards are expected to ship 12-18 months after the standard is finalized.
